MC68HC912DG128 Datasheet, PDF (431/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Appendix: MC68HC912DG128A EEPROM
EEPROM Control Registers
Osc Freq.
16 Mhz
8 Mhz
4 Mhz
2 Mhz
1 Mhz
500 Khz
250 Khz
Table 22-1. EEDIV Selection
Osc Period
62.5ns
125ns
250ns
500ns
1µs
2µs
4µs
Divide Factor
560
280
140
70
35
18
9
EEDIV
$0230
$0118
$008C
$0046
$0023
$0012
$0009
EEMCR — EEPROM Module Configuration
Bit 7
6
5
4
3
NOBDML NOSHW
RESERVED⁽¹⁾
1
RESET:
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
1
1. Bits 4 and 5 have test functions and should not be programmed.
2. Loaded from SHADOW word.
2
EESWAI
1
1
PROTLCK
0
Bit 0
DMY
0
$00F0
NOTE:
Bits[7:4] are loaded at reset from the EEPROM SHADOW word.
The bits 5 and 4 are reserved for test purposes. These locations in
SHADOW word should not be programmed otherwise some locations of
regular EEPROM array will not be more visible.
NOBDML — Background Debug Mode Lockout Disable
0 = The BDM lockout is enabled.
1 = The BDM lockout is disabled.
Loaded from SHADOW word at reset.
Read anytime. Write anytime in special modes (SMODN=0).
NOSHW — SHADOW Word Disable
0 = The SHADOW word is enabled and accessible at address
$0FC0-$0FC1.
1 = Regular EEPROM array at address $0FC0-$0FC1.
Loaded from SHADOW word at reset.
Read anytime. Write anytime in special modes (SMODN=0).
When NOSHW cleared, the regular EEPROM array bytes at address
$0FC0 and $0FC1 are not visible. The SHADOW word is accessed
instead for both read and program/erase operations. Bits[7:4] from
MC68HC912DG128 — Rev 3.0
MOTOROLA
Appendix: MC68HC912DG128A EEPROM
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Technical Data
431