MC68HC912DG128 Datasheet, PDF (410/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Appendix: CGM Practical Aspects
20.4 Practical Aspects For The PLL Usage
20.4.1 Synthesized Bus Frequency
Starting from a ceramic resonator or quartz crystal frequency F_XTAL, if
‘refdv’ and ‘synr’ are the decimal content of the REFDV and SYNR
registers respectively, then the MCU bus frequency will simply be:
F_BUS = F_VCO = ^F----X----^T---₍-^A-r--e-^L--f--^â‹-d--⁽-v--s--y-+---n--1-r--₎--+----1----⁾
synr ∈ {0,1,2,3...63}
refdv ∈ {0,1,2,3...7}
NOTE:
It is not allowed to synthesize a bus frequency that is lower than the
crystal frequency, as the correct functioning of some internal
synchronizers would be jeopardized (e.g. the MCLK and XCLK clock
generators).
20.4.2 Operation Under Adverse Environmental Conditions
The normal operation for the PLL is the so-called ‘automatic bandwidth
selection mode’ which is obtained by having the AUTO bit set in the
PLLCR register. When this mode is selected and as the VCO frequency
approaches its target, the charge pump current level will automatically
switch from a relatively high value of around 40 µA to a lower value of
about 3 µA. It can happen that this low level of charge pump current is
not enough to overcome leakages present at the XFC pin due to adverse
environmental conditions. These conditions are frequently encountered
for uncoated PCBs in automotive applications. The main symptom for
this failure is an unstable characteristic of the PLL which in fact ‘hunts’
between acquisition and tracking modes. It is then advised for the
running software to place the PLL in manual, forced acquisition mode by
clearing both the AUTO and the ACQ bits in the PLLCR register. Doing
so will maintain the high current level in the charge pump constantly and
will permit to sustain higher levels of leakages at the XFC pin. This latest
revision of the Clock Generator Module maintains the lock detection
Technical Data
410
MC68HC912DG128 — Rev 3.0
Appendix: CGM Practical Aspects
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