MC68HC912DG128 Datasheet, PDF (111/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Flash Memory
Flash EEPROM Registers
FEETST — Flash EEPROM Module Test Register
Bit 7
6
5
4
FSTE
GADR
HVT
FENLV
RESET:
0
0
0
0
3
FDISVFP
0
2
VTCK
0
1
STRE
0
Bit 0
MWPR
0
$00F6
In normal mode, writes to FEETST control bits have no effect and always
read zero. The Flash EEPROM module cannot be placed in test mode
inadvertently during normal operation.
FSTE — Stress Test Enable
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
GADR — Gate/Drain Stress Test Select
0 = Selects the drain stress circuitry
1 = Selects the gate stress circuitry
HVT — Stress Test High Voltage Status
0 = High voltage not present during stress test
1 = High voltage present during stress test
FENLV — Enable Low Voltage
0 = Disables low voltage transistor in current reference circuit
1 = Enables low voltage transistor in current reference circuit
FDISVFP — Disable Status V_FP Voltage Lock
When the V_FP pin is below normal programming voltage the Flash
module will not allow writing to the LAT bit; the user cannot erase or
program the Flash module. The FDISVFP control bit enables writing
to the LAT bit regardless of the voltage on the V_FP pin.
0 = Enable the automatic lock mechanism if V_FP is low
1 = Disable the automatic lock mechanism if V_FP is low
MC68HC912DG128 — Rev 3.0
MOTOROLA
Flash Memory
For More Information On This Product,
Go to: www.freescale.com
Technical Data
111