MC68HC912DG128 Datasheet, PDF (413/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Appendix: CGM Practical Aspects
Practical Aspects For The PLL Usage
Table 20-1. Suggested 8MHz Synthesis PLL Filter Elements (Tracking Mode)
Reference [MHz] SYNR Fbus [MHz]
C₀
[nF]
0.614
0.614
0.614
0.614
0.8
0.8
0.8
0.8
1
1
1
1
1.6
1.6
1.6
1.6
2
2
2
2
2.66
2.66
2.66
2.66
4
4
4
4
$0C
7.98
100
$0C
7.98
4.7
$0C
7.98
1
$0C
7.98
0.33
$09
8.00
220
$09
8.00
10
$09
8.00
2.2
$09
8.00
0.47
$07
8.00
220
$07
8.00
10
$07
8.00
2.2
$07
8.00
0.47
$05
8.00
330
$05
8.00
10
$05
8.00
3.3
$05
8.00
1
$03
8.00
470
$03
8.00
22
$03
8.00
4.7
$03
8.00
1
$02
8.00
220
$02
8.00
22
$02
8.00
4.7
$02
8.00
1
$01
8.00
220
$01
8.00
33
$01
8.00
10
$01
8.00
2.2
R₀
[kΩ]
4.3
20
43
75
2.7
12
27
56
2.4
11
24
51
1.5
9.1
15
27
1.1
5.1
11
24
1.5
4.7
10
22
1.2
3
5.6
12
C_p
[kΩ]
10
0.47
0.1
0.033
22
1.0
0.22
0.047
22
1.0
0.22
0.047
33
1.0
0.33
0.1
47
2.2
0.47
0.1
22
2.2
0.47
0.1
22
3.3
1.0
0.22
Loop
Bandwidth
[kHz]
1.1
5.3
11.5
20
0.9
4.2
8.6
19.2
1
4.7
9.9
21.4
1
5.9
10.2
18.6
0.96
4.4
9.6
20.8
1.6
5.1
11
24
1.98
5.1
9.3
19.8
Bandwidth
Limit [kHz]
157
157
157
157
201
201
201
201
251
251
251
251
402
402
402
402
502
502
502
502
668
668
668
668
1005
1005
1005
1005
MC68HC912DG128 — Rev 3.0
MOTOROLA
Appendix: CGM Practical Aspects
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Technical Data
413