MC68HC912DG128 Datasheet, PDF (128/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
EEPROM Memory
8.5 EEPROM Control Registers
EEMCR — EEPROM Module Configuration
Bit 7
6
5
4
3
NOBDML NOSHB
1⁽¹⁾
1⁽¹⁾
1
RESET:
—⁽²⁾
—⁽²⁾
—⁽²⁾
—⁽²⁾
1
1. Bits 4 and 5 have test functions and should not be programmed.
2. Loaded from SHADOW byte.
2
EESWAI
1
1
PROTLCK
0
Bit 0
EERC
0
$00F0
NOTE:
Bits[7:4] are loaded at reset from the EEPROM SHADOW byte.
Bits 5 and 4 are reserved for test purposes. These locations in the
SHADOW byte should not be programmed otherwise some locations in
the regular EEPROM array will no longer be visible.
NOBDML — Background Debug Mode Lockout Disable
0 = The BDM lockout is enabled.
1 = The BDM lockout is disabled.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
NOTE:
NOSHB — SHADOW Byte Disable
0 = SHADOW byte enabled and accessible at address $0FC0.
1 = Regular EEPROM array at address $0FC0.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
When NOSHB cleared, the regular EEPROM array byte at address
$0FC0 is no longer visible. The SHADOW byte is accessed instead
for both read and program/erase operations. BULK, ODD and EVEN
program/erase only apply if the SHADOW byte is enabled.
Bit 6 of the SHADOW byte should not be cleared (set to ‘0’) in order to
have the full EEPROM array visible.
NOTE:
EESWAI — EEPROM Stops in Wait Mode
0 = The module is not affected during WAIT mode
1 = The module ceases to be clocked during WAIT mode
Read and write anytime.
The EESWAI bit should be cleared if the WAIT mode vectors are
mapped in the EEPROM array.
Technical Data
128
MC68HC912DG128 — Rev 3.0
EEPROM Memory
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