MC68HC912DG128 Datasheet, PDF (232/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Capture Timer
BIT 7
6
5
4
3
2
1
BIT 0
$00A2
BIt 7
6
5
4
3
2
1
Bit 0 PACN3 (hi)
$00A3
Bit 7
6
5
4
3
2
1
Bit 0 PACN2 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN3, PACN2 — Pulse Accumulators Count Registers
$00A2, $00A3
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form
the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1
in PACTL, $A0) the PACN3 and PACN2 registers contents are
respectively the high and low byte of the PACA.
When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in
PAFLG ($A1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
BIT 7
6
5
4
3
2
1
BIT 0
$00A4
BIt 7
6
5
4
3
2
1
Bit 0 PACN1 (hi)
$00A5
Bit 7
6
5
4
3
2
1
Bit 0 PACN0 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN1, PACN0 — Pulse Accumulators Count Registers
$00A4, $00A5
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form
the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1
Technical Data
232
MC68HC912DG128 — Rev 3.0
Enhanced Capture Timer
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