MC68HC912DG128 Datasheet, PDF (174/452 Pages) Motorola, Inc – Microcontrollers

Clock Functions
Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
REFDV2 REFDV1 REFDV0
RESET:
0
0
0
0
0
0
0
0
REFDV — Reference Divider Register
$0039
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Bit 7
6
5
4
3
2
1
Bit 0
TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
RESET:
0
0
0
0
0
0
0
0
CGTFLG — Clock Generator Test Register
Always reads zero, except in test modes.
$003A
Bit 7
6
5
4
3
2
1
Bit 0
LOCKIF LOCK
0
0
0
0
LHIF
LHOME
RESET:
0
0
0
0
0
0
0
0
PLLFLG — PLL Flags
$003B
Read anytime, refer to each bit for write conditions.
LOCKIF — PLL Lock Interrupt Flag
0 = No change in LOCK bit.
1 = LOCK condition has changed, either from a locked state to an
unlocked state or vice versa.
To clear the flag, write one to this bit in PLLFLG. Cleared in limp-home
mode.
Technical Data
174
MC68HC912DG128 — Rev 3.0
Clock Functions
For More Information On This Product,
Go to: www.freescale.com
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