MC68HC912DG128 Datasheet, PDF (183/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Functions
Clock Divider Chains
PCLK
5-BIT MODULUS
COUNTER (PR0-PR4)
÷2
÷ 2 REGISTER: SP0BR
BITS: SPR2, SPR1, SPR0
0:0:0
÷2
0:0:1
SPI
BIT RATE
EXTALi
÷2
0:1:0
CLKSRC
÷2
0:1:1
SYSCLK
TO ATD0
and ATD1
MSCAN
CLOCK
÷2
1:0:0
÷2
1:0:1
÷2
1:1:0
÷2
1:1:1
ECLK
BCLK
CLKSW
SYNCHRONIZER
BKGD IN
BKGD
PIN
LOGIC
BKGD DIRECTION
BKGD OUT
BDM BIT CLOCK:
Receive: Detect falling edge,
count 12 ECLKs, Sample input
Transmit 1: Detect falling edge,
count 6 ECLKs while output is
high impedance, Drive out 1 E
cycle pulse high, high imped-
ance output again
Transmit 0: Detect falling edge,
Drive out low, count 9 ECLKs,
Drive out 1 E cycle pulse high,
high impedance output
Figure 11-9. Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM
MC68HC912DG128 — Rev 3.0
MOTOROLA
Clock Functions
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Technical Data
183