MC68HC912DG128 Datasheet, PDF (368/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
The user should be careful that the state of the BDMACT bit is not
unintentionally changed with the WRITE_NEXT firmware command.
If it is unintentionally changed from 1 to 0, it will cause a system
runaway because it would disable the BDM firmware ROM while the
CPU12 was executing BDM firmware. The following two commands
show how BDMACT may unintentionally get changed from 1 to 0.
WRITE_X with data $FEFE
WRITE_NEXT with data $C400
The first command writes the data $FEFE to the X index register. The
second command writes the data $C4 to the $FF00 INSTRUCTION
register and also writes the data $00 to the $FF01 STATUS register.
ENTAG — Tagging Enable
Set by the TAGGO command and cleared when BDM mode is
entered. The serial system is disabled and the tag function enabled
16 cycles after this bit is written.
0 = Tagging not enabled, or BDM active.
1 = Tagging active. BDM cannot process serial commands while
tagging is active.
SDV — Shifter Data Valid
Shows that valid data is in the serial interface shift register. Used by
the BDM firmware.
0 = No valid data. Shift operation is not complete.
1 = Valid Data. Shift operation is complete.
TRACE — Asserted by the TRACE1 command
CLKSW — Clock Switch
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM communications.
If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
Technical Data
368
MC68HC912DG128 — Rev 3.0
Development Support
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