MC68HC912DG128 Datasheet, PDF (287/452 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Inter-IC Bus
IIC Register Descriptions
5. A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a one to it.
SRW — Slave Read/Write
When IAAS is set this bit indicates the value of the R/W command bit
of the calling address sent from the master.
CAUTION:
This bit is only valid when the IIC is in slave mode, a complete address
transfer has occurred with an address match and no other transfers have
been initiated.
Checking this bit, the CPU can select slave transmit/receive mode
according to the command of the master.
0 = Slave receive, master writing to slave
1 = Slave transmit, master reading from slave
IBIF — IIC Bus Interrupt Flag
The IBIF bit is set when an interrupt is pending, which will cause a
processor interrupt request provided IBIE is set. IBIF is set when one
of the following events occurs:
1. Complete one byte transfer (set at the falling edge of the 9th
clock).
2. Receive a calling address that matches its own specific address in
slave receive mode.
3. Arbitration lost.
This bit must be cleared by software, writing a one to it, in the interrupt
routine.
RXAK — Received Acknowledge
The value of SDA during the acknowledge bit of a bus cycle. If the
received acknowledge bit (RXAK) is low, it indicates an acknowledge
signal has been received after the completion of 8 bits data
transmission on the bus. If RXAK is high, it means no acknowledge
signal is detected at the 9th clock.
0 = Acknowledge received
1 = No acknowledge received
MC68HC912DG128 — Rev 3.0
MOTOROLA
Inter-IC Bus
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Technical Data
287