HC1S25 Datasheet, PDF (99/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
Figure 6–4. HardCopy Stratix Device Floorplan with Soft Region Off
Using Analysis and Synthesis Settings for Performance
Improvement
After establishing the baseline for improvement for this design of
65.30 MHz FPGA/88.14 MHz HardCopy, you can gain additional
performance improvement in the Stratix FPGA and HardCopy Stratix
devices using the available features in the Quartus II software.
Changing the Analysis & Synthesis Effort from Balanced to Speed
yields additional benefit in performance, but at the cost of additional LE
resources. The Tcl command for this assignment is as follows:
set_global_assignment -name
STRATIX_OPTIMIZATION_TECHNIQUE SPEED
Altera Corporation
September 2008
6–11