HC1S25 Datasheet, PDF (104/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
Additional correlation is seen inside the <project>.dse.rpt file, showing
the summary of assignments used for each compile inside the Quartus II
software. The base compile settings and the fifth compile settings show
good correlation, as shown in Table 6–6. The MUX_RESTRUCTURE setting
did not have any effect on the design performance. This may be due to an
already efficient HDL coding for multiplexer structures, requiring no
optimization.
Table 6–6. Base Compile and Fifth Compile Correlation
Setting
PHYSICAL_SYNTHESIS_REGISTER_RETIMING
SEED
STATE_MACHINE_PROCESSING
MUX_RESTRUCTURE
PHYSICAL_SYNTHESIS_COMBO_LOGIC
FITTER_EFFORT
AUTO_PACKED_REGISTERS_STRATIX
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION
ADV_NETLIST_OPT_SYNTH_GATE_RETIME
STRATIX_OPTIMIZATION_TECHNIQUE
PHYSICAL_SYNTHESIS_EFFORT
New Value
ON
1
AUTO
OFF
ON
STANDARD FIT
NORMAL
ON
ON
SPEED
EXTRA
Base Value
ON
1
AUTO
AUTO
ON
STANDARD FIT
NORMAL
ON
ON
SPEED
EXTRA
The information presented in Table 6–6 confirms that the FPGA Prototype
device has been optimized as much as possible without manual floorplan
adjustments.
Design Space Explorer for HardCopy Stratix Devices
Migrating this compiled design to the HardCopy Stratix project and
compiling the HardCopy Stratix design optimization, results in a design
performance of 92.01 MHz. The next task is to run DSE on the HardCopy
Stratix project using Low Effort (Seed Sweep) in the Exploration
Settings, and entering a range of seed numbers with which to compile the
project.
6–16
Altera Corporation
September 2008