HC1S25 Datasheet, PDF (5/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Features
■ Supports high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,
double data rate (DDR) SDRAM, DDR fast-cycle RAM (FCRAM),
and single data rate (SDR) SDRAM
■ Support for multiple intellectual property (IP) megafunctions from
Altera^® MegaCore^® functions, and Altera Megafunction Partners
Program (AMPP^SM) megafunctions
■ Available in space-saving flip-chip FineLine BGA^® and wire-bond
packages (Tables 1–2 and 1–3)
■ Optional emulation of original FPGA configuration sequence
■ Optional instant-on power-up
1 The actual performance and power consumption improvements
over the Stratix equivalents mentioned in this data sheet are
design-dependent.
Table 1–2. HardCopy Stratix Device Package Options and I/O Pin Counts
Note (1)
Device
HC1S25
HC1S30
HC1S40
HC1S60
HC1S80
672-Pin
780-Pin
1,020-Pin
FineLine BGA (2) FineLine BGA (3) FineLine BGA (3)
473
597
613 (4)
782
782
Notes to Table 1–2:
(1) Quartus II I/O pin counts include one additional pin, PLLENA, which is not a
general-purpose I/O pin. PLLENA can only be used to enable the PLLs.
(2) This device uses a wire-bond package.
(3) This device uses a flip-chip package.
(4) In the Stratix EP1S40F780 FPGA, the I/O pins U12 and U18 are general-purpose
I/O pins. In the FPGA prototype,
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE, and in the HardCopy Stratix
HC1S40F780 device, U12 and U18 must be connected to ground. The
EP1S40F780_HARDCOPY_FPGA_PROTOTYPE and HC1S40F780 pin-outs are
identical.
Altera Corporation
September 2008
1–3
Preliminary