HC1S25 Datasheet, PDF (54/110 Pages) Altera Corporation – HardCopy Stratix Device Family

PLL Specifications
Table 4–50. High-Speed I/O Specifications (Part 2 of 2) Notes (1), (2)
Symbol
Conditions
Performance
Unit
Min
Typ
Max
Input jitter tolerance
All
(peak-to-peak)
250
ps
Output jitter (peak-to-peak)
All
160
ps
Output t_RISE
LVDS
80
110
120
ps
HyperTransport technology
110
170
200
ps
LVPECL
90
130
150
ps
PCML
80
110
135
ps
Output t_FALL
LVDS
80
110
120
ps
HyperTransport technology
110
170
200
ps
LVPECL
90
130
160
ps
PCML
105
140
175
ps
t_DUTY
LVDS (J = 2 through 10)
47.5
50
52.5
%
LVDS (J =1) and LVPECL,
45
50
55
%
PCML, HyperTransport
technology
t_LOCK
All
100
μs
Notes to Table 4–50:
(1) When J = 4, 7, 8, and 10, the SERDES block is used.
(2) When J = 2 or J = 1, the SERDES is bypassed.
PLL
Specifications
Table 4–51 describes the HardCopy Stratix device enhanced PLL
specifications.
Table 4–51. Enhanced PLL Specifications (Part 1 of 3)
Symbol
f_IN
f_{INDU TY}
f_EINDUTY
t_INJITTER
t_{E INJI TTE R}
t_FCOMP
Parameter
Min Typ
Input clock frequency
3 (1)
Input clock duty cycle
40
External feedback clock input duty
40
cycle
Input clock period jitter
External feedback clock period jitter
External feedback clock compensation
time (3)
Max
684
60
60
±200 (2)
±200 (2)
6
Unit
MHz
%
%
ps
ps
ns
4–30
Altera Corporation
September 2008