HC1S25 Datasheet, PDF (41/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Table 4–33 shows the external I/O timing parameters when using global
clock networks.
Table 4–33. HardCopy Stratix Global Clock External I/O Timing Parameters
Notes (1), (2)
Symbol
Parameter
t_INSU
Setup time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
t_INH
Hold time for input or bidirectional pin using IOE input register with
global clock fed by CLK pin
t_OUTCO
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by CLK pin
t_{INS UPL L}
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
t_INHPLL
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
t_OUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
t_XZPLL
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
t_ZXPLL
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Notes to Table 4–33:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column and row IOE pins. Designers should use
the Quartus II software to verify the external timing for any pin.
HardCopy Stratix External I/O Timing
These timing parameters are for both column IOE and row IOE pins. In
HC1S30 devices and above, designers can decrease the t_SU time by using
FPLLCLK, but may get positive hold time in HC1S60 and HC1S80
devices. Designers should use the Quartus II software to verify the
external devices for any pin.
Altera Corporation
September 2008
4–17