HC1S25 Datasheet, PDF (100/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
The relevant compilation results of the FPGA are provided in Table 6–2.
Table 6–2. Relevant Compile Results
Result Type
f_MAX
Total logic elements
Total LABs
M512 blocks
M4K blocks
M-RAM blocks
Total memory bits
Total RAM block bits
DSP block 9-bit elements
Results
68.88 MHz
5,508/32,470 (16%)
598/3,247 (18%)
20/295 (6%)
16/171 (9%)
0/2 (0%)
74,752/2,137,536 (3%)
85,248/2,137,536 (3%)
2/96 (2%)
Increasing the LE resources by 6% only yielded an additional 3 MHz in
performance in the FPGA, without using additional settings. However,
after migrating this design to the HardCopy Stratix design and compiling
it, the performance did not improve over the previous HardCopy Stratix
design compile, and was slightly worse in performance at 87.34 MHz.
This shows that the Quartus II software synthesis was very effective with
the Synthesis Effort Level set to Balanced, and there was only marginal
improvement in the FPGA when this option was set to Speed.
The next settings activated in this example were the Synthesis Netlist
Optimizations shown below in Tcl format for WYSIWYG synthesis
remapping and gate-level retiming after synthesis mapping:
set_global_assignment -name
ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name
ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
6–12
Altera Corporation
September 2008