HC1S25 Datasheet, PDF (58/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Electrostatic Discharge
Figure 4–2 shows a transistor level cross section of the HardCopy Stratix
CMOS I/O buffer structure which will be used to explain ESD protection.
Figure 4–2. Transistor-Level Cross Section of the HardCopy Stratix Device I/O Buffers
Core
Signal
VPAD
Core Signal OR
the Larger of
VCCIO or VPAD
The Larger of
VCCIO or VPAD
VCCIO
Ensures 3 V
Tolerance and
Hot-Insertion
Protection
n+
n+
p-well
p+
p+
n+
n-well
p-substrate
The CMOS output drivers in the I/O pins intrinsically provide
electrostatic discharge protection. There are two cases to consider for ESD
voltage strikes: positive voltage zap and negative voltage zap.
Positive Voltage Zap
A positive ESD voltage zap occurs when a positive voltage is present on
an I/O pin due to an ESD charge event. This can cause the N+ (Drain)/P-
Substrate) junction of the N-channel drain to break down and the N+
(Drain)/P-Substrate/N+ (Source) intrinsic bipolar transistor turns ON to
discharge ESD current from I/O pin to GND.
4–34
Altera Corporation
September 2008