HC1S25 Datasheet, PDF (90/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Planning Stratix FPGA Design for HardCopy Stratix Design Conversion
Planning Stratix
FPGA Design for
HardCopy Stratix
Design
Conversion
In order to achieve greater performance improvement in your HardCopy
Stratix device, additional Quartus II software constraints and placement
techniques in the HARDCOPY_FPGA_PROTOTYPE design project may
be necessary. This does not mean changing the source hardware
description language (HDL) code or functionality, but providing
additional constraints in the Quartus II software that specifically impact
HardCopy Stratix timing optimization.
Planning ahead for migration to the HardCopy design, while still
modifying the HARDCOPY_FPGA_PROTOTYPE design, can improve
design performance results. You must anticipate how portions of your
FPGA design are placed and connected in the HardCopy device
floorplan. The HardCopy device floorplan is smaller than the FPGA
device floorplan, allowing use of the customized metal routing in
HardCopy Stratix devices.
Partitioning Your Design
Partitioning your design into functional blocks is essential in
multi-million gate designs. With a HardCopy Stratix device, you can
implement approximately one million ASIC gates of logic. Therefore,
Altera recommends hierarchical-design partitioning based on system
functions.
When using a hierarchical- or incremental-design methodology, you
must consider how your design is partitioned to achieve good results.
Altera recommends the following practices for partitioning designs as
documented in the Design Recommendations for Altera Devices chapter in
volume 1 of the Quartus II Development Software Handbook:
■ Partition your design at functional boundaries.
■ Minimize the I/O connections between different partitions.
■ Register all inputs and outputs of each block. This makes logic
synchronous and avoids glitches and any delay penalty on signals
that cross between partitions. Registering I/O pins typically
eliminates the need to specify timing requirements for signals that
connect between different blocks.
■ Do not use glue logic or connection logic between hierarchical
blocks. When you preserve hierarchy boundaries, glue logic is not
merged with hierarchical blocks. Your synthesis software may
optimize glue logic separately, which can degrade synthesis results
and is not efficient when used with the LogicLock design
methodology.
■ Logic is not synthesized or optimized across partition boundaries.
Any constant values (for example, signals set to GND), are not
propagated across partitions.
6–2
Altera Corporation
September 2008