HC1S25 Datasheet, PDF (68/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Series Handbook, Volume 1
Figure 5–1. HardCopy Stratix and HardCopy APEX Design Flow Diagram
Start Quartus HardCopy Flow
Stratix
Select FPGA Family
Select Stratix
HARDCOPY_FPGA_PROTOTYPE
Device
One Step Process ⁽³⁾
Compile
Mirgrate the
Compiled Project
Migrate Only ⁽¹⁾
Two Step Process ⁽²⁾
Migrate the
Compiled Project
Compile
Migrate the
Compiled Project
Close the Quartus II
FPGA Project
Close the Quartus II
FPGA Project
Close the Quartus II
FPGA Project
APEX
Select APEX FPGA
Device Supported by
HardCopy APEX
Compile
Open the Quartus II
HardCopy Project
Open the Quartus II
HardCopy Project
Open the Quartus II
HardCopy Project
Compile to HardCopy
Stratix Device (Actual
HardCopy Floorplan)
Compile to HardCopy
Stratix Device (Actual
HardCopy Floorplan)
Compile to HardCopy
Stratix Device (Actual
HardCopy Floorplan)
Placement
Info for
HardCopy
Run HardCopy Files
Wizard (Quartus II
Archive File for
delivery to Altera)
Notes to Figure 5–1:
(1) Migrate Only Process: The displayed flow is completed manually.
(2) Two Step Process: Migration and Compilation are done automatically (shaded area).
(3) One Step Process: Full HardCopy Compilation. The entire process is completed automatically (shaded area).
The Design Flow Steps of the One Step Process
The following sections describe each step of the full HardCopy
compilation (the One Step Process), Figure 5–1.
Compile the Design for an FPGA
This step compiles the design for a HARDCOPY_FPGA_PROTOTYPE
device and gives you the resource utilization and performance of the
FPGA.
5–6
Preliminary
Altera Corporation
September 2008