HC1S25 Datasheet, PDF (59/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
The dashed line (Figure 4–3) shows the ESD current discharge path
during a positive voltage zap.
Figure 4–3. ESD Protection During Positive Voltage Zap
IO
Source
PMOS
Gate
N+ ^D
Drain
IO
Drain
P-Substrate
G
Gate
NMOS
N+ ^S
Source
GND
GND
Negative Voltage Zap
When the I/O pin receives a negative ESD zap at the pin that is less than
-0.7 V (0.7 V is the voltage drop across a diode), the intrinsic
PSubstrate/N+ drain diode is forward biased. Hence, the discharge ESD
current path is from GND to the I/O pin, as shown in Figure 4–4.
Altera Corporation
September 2008
4–35