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HC1S25 Datasheet, PDF (45/110 Pages) Altera Corporation – HardCopy Stratix Device Family | |||
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Operating Conditions
Tables 4â40 through 4â41 show the external timing parameters on column
and row pins for HC1S60 devices.
Table 4â40. HC1S60 External I/O Timing on Column Pins Using Global Clock
Networks
Parameter
tINSU
tINH
tOUTCO
tXZ
tZX
tINS UPL L
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
Performance
Unit
Min
Max
2.000
ns
0.000
ns
3.051
6.977
ns
2.991
6.853
ns
2.991
6.853
ns
1.315
ns
0.000
ns
1.029
2.323
ns
0.969
2.199
ns
0.969
2.199
ns
Table 4â41. HC1S60 External I/O Timing on Row Pins Using Global Clock
Networks
Parameter
tINSU
tINH
tOUTCO
tXZ
tZX
tINS UPL L
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
Performance
Min
Max
2.232
0.000
3.182
3.209
3.209
1.651
0.000
1.154
1.181
1.181
7.286
7.354
7.354
2.622
2.690
2.690
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Altera Corporation
September 2008
4â21
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