HC1S25 Datasheet, PDF (57/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Table 4–52 describes the HardCopy Stratix device fast PLL
specifications.
Table 4–52. Fast PLL Specifications
Symbol
f_IN
f_OUT
f_{OUT_EXT}
f_VCO
t_{INDU TY}
t_INJITTER
t_DUTY
t_JITTER
t_LOCK
m
l0, l1, g0
t_ARESET
Parameter
Min
CLKIN frequency (for m = 1) (1), (2)
300
CLKIN frequency (for m = 2 to 19)
300/
m
CLKIN frequency (for m = 20 to 32)
10
Output frequency for internal global or 9.4
regional clock (3)
Output frequency for external clock (2) 9.375
VCO operating frequency
300
CLKIN duty cycle
40
Period jitter for CLKIN pin
Duty cycle for DFFIO 1× CLKOUT pin (4) 45
Period jitter for DFFIO clock out (4)
Period jitter for internal global or
regional clock
Time required for PLL to acquire lock 10
Multiplication factors for m counter (4) 1
Multiplication factors for l0, l1, and g0
1
counter (5), (6)
Minimum pulse width on areset
10
signal
Max
717
1,000/m
1,000/m
420
717
1,000
60
±200
55
±80
±100 ps for >200-MHz outclk
±20 mUI for <200-MHz outclk
100
32
32
Unit
MHz
MHz
MHz
MHz
MHz
MHz
%
ps
%
ps
ps or
mUI
μs
Integer
Integer
ns
Notes to Table 4–52:
(1) Refer to “Maximum Input and Output Clock Rates” on page 4–23 for more information.
(2) PLLs 7, 8, 9, and 10 in the HC1S80 device support up to 717-MHz input and output.
(3) When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to
the global or regional clocks (for example, the maximum data rate 840 Mbps divided by the smallest SERDES J
factor of 4).
(4) This parameter is for high-speed differential I/O mode only.
(5) These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
(6) High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
Electrostatic
Discharge
Electrostatic discharge (ESD) protection is a design practice that is
integrated in Altera FPGAs and Structured ASIC devices. HardCopy
Stratix devices are no exception, and they are designed with ESD
protection on all I/O and power pins.
Altera Corporation
September 2008
4–33