HC1S25 Datasheet, PDF (43/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Tables 4–36 through 4–37 show the external timing parameters on column
and row pins for HC1S30 devices.
Table 4–36. HC1S30 External I/O Timing on Column Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Min
Max
1.935
0.000
2.814
2.754
2.754
1.265
0.000
1.068
1.008
1.008
7.274
7.159
7.159
2.423
2.308
2.308
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4–37. HC1S30 External I/O Timing on Row Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
1.995
ns
0.000
ns
2.917
7.548
ns
2.944
7.630
ns
2.944
7.630
ns
1.337
ns
0.000
ns
1.164
2.672
ns
1.191
2.754
ns
1.191
2.754
ns
Altera Corporation
September 2008
4–19