HC1S25 Datasheet, PDF (55/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Table 4–51. Enhanced PLL Specifications (Part 2 of 3)
Symbol
f_OUT
f_{OUT_EXT}
t_OUTDUTY
t_JITTER
t_CONFIG5,6
t_{CO NFIG 11,1 2}
t_{S CANCL K}
t_{DL OCK}
t_LOCK
f_VCO
t_LSKEW
t_SKEW
f_SS
% spread
Parameter
Min Typ
Output frequency for internal global or 0.3
regional clock
Output frequency for external clock (2) 0.3
Duty cycle for external clock output
45
(when set to 50%)
Period jitter for external clock output (5)
Time required to reconfigure the scan
chains for PLLs 5 and 6
Time required to reconfigure the scan
chains for PLLs 11 and 12
scanclk frequency (4)
Time required to lock dynamically (after (8)
switchover or reconfiguring any non-
post-scale counters/delays) (6)
Time required to lock from end of
10
device configuration
PLL internal VCO operating range
300
Clock skew between two external clock
±50
outputs driven by the same counter
Clock skew between two external clock
±75
outputs driven by the different counters
with the same settings
Spread spectrum modulation frequency 30
Percentage spread for spread
spectrum frequency (9)
0.4 0.5
Max
500
526
55
±100 ps for >200 MHz outclk
±20 mUI for <200 MHz outclk
289/f_SCANCLK
193/f_SCANCLK
22
100
400
800 (7)
150
0.6
Unit
MHz
MHz
%
ps or
mUI
MHz
μs
μs
MHz
ps
ps
kHz
%
Altera Corporation
September 2008
4–31