HC1S25 Datasheet, PDF (103/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
Running the HardCopy Timing Optimization wizard on this design and
compiling the HardCopy Stratix project yields an f_MAX of 92.01 MHz,
a 24% improvement over the FPGA timing.
Design Space Explorer
The available Fitter Settings produce an additional performance
improvement. The DSE feature is used on the Stratix FPGA device to run
through the various seeds in the design and select the best seed point to
use for future compiles. This can often yield additional performance
benefits as the Quartus II software further refines placement of the LEs
and performs clustering of associated logic together.
For this design example, DSE was run with high effort (physical
synthesis) and multiple placement seeds. Table 6–5 shows the DSE
results. The base compile matches the fifth compile in the DSE variations,
showing that the work already done on the design before DSE was
optimal. The FPGA project was optimized before running DSE.
Table 6–5. DSE Results
Compile Point
Base (Best)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Clock Period: CLK
13.451 ns (74.34 MHz)
13.954 ns
13.712 ns
14.615 ns
13.911 ns
13.451 ns
14.838 ns
14.177 ns
14.479 ns
14.863 ns
14.662 ns
14.250 ns
14.016 ns
13.840 ns
13.681 ns
14.829 ns
Logic Cells
5,781
5,703
6,447
5,777
5,742
5,781
5,407
5,751
5,827
5,596
5,605
5,710
5,708
5,802
5,788
5,644
Altera Corporation
September 2008
6–15