HC1S25 Datasheet, PDF (102/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
for Speed. The Fitter effort is set to Standard Fit (highest effort). The
next features enabled are the Physical Synthesis Optimizations as seen
in the Tcl assignments below and in Figure 6–5:
set_global_assignment -name
PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name
PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name
PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT
EXTRA
Figure 6–5. Physical Synthesis Optimization Settings
The compiled design shows a performance increase in the FPGA, running
at an f_MAX of 74.34 MHz, requiring additional LE resources as a result of
the physical synthesis and logic duplication. In this example, you can see
how performance can be increased in the Stratix FPGA device at the
expense of additional LE resources, as this design’s LE resources grew
almost 12% over the beginning compilation. The compiled FPGA
design’s statistics are provided in Table 6–4.
Table 6–4. Compiled FPGA Design Statistics
Result Type
f_MAX
Total logic elements
Total LABs
Results
74.34 MHz
5,781/32,470 (17%)
610/3,247 (18%)
6–14
Altera Corporation
September 2008