HC1S25 Datasheet, PDF (12/110 Pages) Altera Corporation – HardCopy Stratix Device Family

DSP Blocks
DSP Blocks
DSP blocks in HardCopy Stratix devices are architecturally identical to
those in Stratix devices. The number of DSP blocks available in
HardCopy Stratix devices matches the number of DSP blocks available in
the corresponding Stratix device.
PLLs and Clock
Networks
The PLLs in HardCopy Stratix devices are identical to those in Stratix
devices. The clock networks are also implemented exactly as they are in
Stratix devices. The number of PLLs can vary between corresponding
Stratix and HardCopy Stratix devices. Table 2–5 shows the number of
PLLs available in each device.
Table 2–5. HardCopy Stratix and Stratix PLL Comparison
HardCopy Stratix
Stratix
Device
HC1S25
HC1S30
HC1S40
HC1S60
EP1S830
PLLs
6
6
6
12
12
Device
EP1S25
EP1S30
EP1S40
EP1S60
EP1S830
PLLs
6
10
12
12
12
Table 2–6 illustrates the differences between HardCopy Stratix and
Stratix PLLs.
Table 2–6. HardCopy Stratix and Stratix PLL Differences
HardCopy Stratix
Stratix
HC1S30 and HC1S40 devices have six HC1S30 devices have 10 PLLs.
PLLs.
HC1S40 devices have12 PLLs.
PLL dynamic reconfiguration uses
ROM for information. This
reconfiguration is performed in the
back-end and does not affect the
migration flow.
PLL dynamic reconfiguration uses a
MIF to initialize a RAM resource with
information.
I/O Structure and
Features
The HardCopy Stratix IOEs are equivalent, but not identical to, the Stratix
FPGA IOEs. This is due to the reduced die size, layout difference, and
metal customization of the HardCopy Stratix device. The differences are
minor but may be relevant to customers designing with tight DC and
switching characteristics. However, no signal integrity concerns are
introduced with HardCopy Stratix IOEs.
2–6
Altera Corporation
September 2008