HC1S25 Datasheet, PDF (67/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Design Flow
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Stratix FPGA for your design. The three devices are tied together with the
same netlist, thus a single SRAM Object File (.sof) can be used to achieve
the various goals at each stage. The same SRAM Object File is generated
in the HARDCOPY_FPGA_PROTOTYPE design, and is used to program
the Stratix FPGA device, the same way that it is used to generate the
HardCopy Stratix device, guaranteeing a seamless migration.
For more information about the SRAM Object File and programming
Stratix FPGA devices, refer to the Programming and Configuration chapter
of the Introduction to Quartus II Manual.
HardCopy
Design Flow
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Figure 5–1 shows a HardCopy design flow diagram. The design steps are
explained in detail in the following sections of this chapter. The
HardCopy Stratix design flow utilizes the HardCopy Timing
Optimization Wizard to automate the migration process into a one-step
process. The remainder of this section explains the tasks performed by
this automated process.
For a detailed description of the HardCopy Timing Optimization Wizard
and HardCopy Files Wizard, refer to “HardCopy Timing Optimization
Wizard Summary” and “Generating the HardCopy Design Database”.
Altera Corporation
September 2008
5–5
Preliminary