HC1S25 Datasheet, PDF (22/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Series Handbook, Volume 1
Table 3–4 shows the JTAG timing parameters and values for HardCopy
Stratix devices.
Table 3–4. HardCopy Stratix JTAG Timing Parameters and Values
Symbol
Parameter
Min Max Unit
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
t_JSSU
t_JSH
t_JSCO
t_JSZX
t_JSXZ
TCK clock period
100
ns
TCK clock high time
50
ns
TCK clock low time
JTAG port setup time
50
ns
20
ns
JTAG port hold time
45
ns
JTAG port clock to output
25 ns
JTAG port high impedance to valid output
25 ns
JTAG port valid output to high impedance
25 ns
Capture register setup time
20
ns
Capture register hold time
45
ns
Update register clock to output
35 ns
Update register high impedance to valid output
35 ns
Update register valid output to high impedance
35 ns
f
For more information on JTAG, refer to AN 39: IEEE Std. 1149.1 (JTAG)
Boundary-Scan Testing in Altera Devices.
Document
Table 3–5 shows the revision history for this chapter.
Revision History
Table 3–5. Document Revision History (Part 1 of 2)
Date and Document
Version
Changes Made
September 2008
v3.4
Updated chapter number and metadata.
June 2007 v3.3
Updated Figure 3–1.
December 2006
v3.2
Updated revision history.
March 2006
Formerly chapter 7; no content change.
Summary of Changes
—
—
—
—
3–4
Preliminary
Altera Corporation
September 2008