HC1S25 Datasheet, PDF (106/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
Figure 6–6. Vertically Stretched LogicLock Region
This floorplan would be better optimized if the LogicLock region had a
more square shape, helping the paths that go from memory-to-memory,
by containing the M4K and M512 memory blocks in a smaller space, and
allowing LAB placement to be adjusted by the Fitter. In the HardCopy
Stratix device, signals are routed between LABs, DSP blocks, and
memory blocks using the customized metal layers. The reconfigurable
routing tracks in the Stratix FPGA device limit the routing paths and
delays between elements in the HardCopy Stratix device. This flexibility
allows for aspect ratio changes in LogicLock regions, so the raw distance
between points becomes the critical factor, and not the usage of available
routing resources in the FPGA.
For the final placement optimization in this example, the LogicLock
region was fixed in a square region that encompassed two columns of
M4K blocks, four columns of M512 blocks, two columns of DSP blocks,
and enough LABs to fit the remaining resources required. After
compiling the design with these new LogicLock assignments, the
performance increased to 93.46 MHz in the HardCopy Stratix device. The
critical path and LogicLock region location can be seen in the zoomed-in
area of the floorplan (Figure 6–7).
You can see in Figure 6–7 that the critical path shown is from an M4K
block to an M512 block through several levels of logic. The placement of
the memory blocks can be optimized manually, since the LogicLock
region contains more memory blocks than necessary.
6–18
Altera Corporation
September 2008