HC1S25 Datasheet, PDF (9/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Description, Architecture, and Features
Table 2–1 illustrates the differences between HardCopy Stratix and
Stratix devices.
Table 2–1. HardCopy Stratix and Stratix Device Comparison (Part 1 of 2)
HardCopy Stratix
Stratix
Customized device. All
Re-programmable with configuration is
reprogrammability support is removed required upon power-up.
and no configuration is required.
Average of 50% performance
improvement over corresponding
FPGA (1).
High-performance FPGA.
Average of 40% less power
consumption compared to
corresponding FPGA (1).
Standard FPGA power consumption.
Contact Altera for information regarding IP support for all devices is available.
specific IP support.
Double data rate (DDR) SDRAM
maximum operating frequency is
pending characterization.
DDR SDRAM can operate at 200 MHz
for -5 speed grade devices.
All routing connections are direct and MultiTrack™ routing stitches together
all unused routing is removed.
routing resources to provide a path.
HC1S30 and HC1S40 devices have
two M-RAM blocks. HC1S80 devices
have six M-RAM blocks.
EP1S30 and EP1S40 devices have four
M-RAM blocks. EP1S80 devices have
nine M-RAM blocks.
It is not possible to initialize M512 and
M4K RAM contents during power-up.
The contents of M512 and M4K RAM
blocks can be preloaded during
configuration with data specified in a
memory initialization file (.mif).
The contents of memory output
registers are unknown after power-on
reset (POR).
The contents of memory output
registers are initialized to '0' after POR.
HC1S30 and HC1S40 devices have six HC1S30 devices have 10 PLLs.
PLLs.
HC1S40 devices have 12 PLLs.
PLL dynamic reconfiguration uses
ROM for information. This
reconfiguration is performed in the
back-end and does not affect the
migration flow.
PLL dynamic reconfiguration uses a
MIF to initialize a RAM resource with
information.
The I/O elements (IOEs) are equivalent
but not identical to FPGA IOEs due to
slight design optimizations for
HardCopy devices.
The IOEs are optimized for the FPGA
architecture.
Altera Corporation
2–3
September 2008