HC1S25 Datasheet, PDF (15/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HARDCOPY_
FPGA_
PROTOTYPE
Devices
Description, Architecture, and Features
drive signals into the device before or during power up or power down
without damaging the device. HardCopy Stratix devices do not drive out
until they have attained proper operating conditions.
You can power up or power down the V_CCIO and V_CCINT pins in any
sequence. The power supply ramp rates can range from 100 ns to 100 ms.
During hot socketing, the I/O pin capacitance is less than 15 pF and the
clock pin capacitance is less than 20 pF.
■ The hot socketing DC specification is | I_IOPIN | < 300 µA.
■ The hot socketing AC specification is | I_IOPIN | < 8 mA for 10 ns or
less. This specification takes into account the pin capacitance only.
Additional capacitance for trace, connector, and loading needs to be
taken into consideration separately. I_IOPIN is the current at any user
I/O pin on the device.
1 The DC specification applies when all V_CC supplies to the device
are stable in the powered-up or powered-down conditions. For
the AC specification, the peak current duration due to power-up
transients is 10 ns or less.
HARDCOPY_FPGA_PROTOTYPE devices are Stratix FPGAs available
for designers to prototype their HardCopy Stratix designs and perform
in-system verification before migration to a HardCopy Stratix device. The
HARDCOPY_FPGA_PROTOTYPE devices have the same available
resources as in the final HardCopy Stratix devices.
The Quartus II software version 4.1 and later contains the latest timing
models. For designs with tight timing constraints, Altera strongly
recommends compiling the design with the Quartus II software
version 4.1 or later. To properly verify I/O features, it is important to
design with the HARDCOPY_FPGA_PROTOTYPE device option prior to
migrating to a HardCopy Stratix device.
Altera Corporation
2–9
September 2008