HC1S25 Datasheet, PDF (48/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
Table 4–45. HardCopy Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11]
Pins and FPLL[10..7]CLK Pins
I/O Standard
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
GTL
GTL+
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
SSTL-18 class I
SSTL-18 class II
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
Differential HSTL
LVPECL (1)
PCML (1)
LVDS (1)
HyperTransport
technology (1)
Performance
422
422
422
422
422
300
300
400
400
400
400
400
400
400
400
400
400
422
422
422
422
422
300
400
717
400
717
717
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–24
Altera Corporation
September 2008