HC1S25 Datasheet, PDF (93/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Altera Corporation
September 2008
Design Guidelines for HardCopy Stratix Performance Improvement
turned on by default in the HardCopy Stratix design. While this does
allow the Fitter to place all logic in your design with fewer restrictions, it
is not optimal for performance improvement in the HardCopy Stratix
design.
Recommended LogicLock Settings for HardCopy Stratix Designs
Altera recommends the following LogicLock region settings for the
HARDCOPY_FPGA_PROTOTYPE:
■ Turn on Reserve Unused Logic
■ Turn off Soft Region
■ Select either Auto or Fixed as the Size (design-dependent)
■ Select either Floating or Locked as the Location (design-dependent)
When using the Reserve Unused Logic setting in a design with high
resource utilization (> 95% LE utilization), and a large number of
LogicLock regions, the design may not fit in the device. Turning off
Reserve Unused Logic in less critical LogicLock regions can help Fitter
placement. The LEs allowed to float in placement and be packed into
unused LEs of LogicLock regions may not be placed optimally after
migration to the HardCopy Stratix device since they are merged with
other LogicLock regions.
After running the HardCopy Timing Optimization Wizard, the
LogicLock region properties are reset to their default conditions. This
allows a successful and immediate placement of your design in the
Quartus II software. You can further refine the LogicLock region
properties for additional benefits.
Altera recommends using the following properties for LogicLock regions
in the HardCopy design project:
■ Turn off Soft Region
■ Select either Auto or Fixed as the Size after you are satisfied with the
placement and timing result of a LogicLock region in a successful
HardCopy Stratix compilation
■ Select either Floating or Locked as the Location after you are
satisfied with the placement and timing results
■ Reserve Unused Logic is not applicable in the HardCopy Stratix
device placement because logic array block (LAB) contents can not
be changed after the HardCopy Timing Optimization Wizard is run
An example of a well partitioned design using LogicLock regions
effectively for some portions of the design is shown in Figure 6–1. Only
the most critical logic functions required are placed in LogicLock regions
in order to achieve the desired performance in the HardCopy Stratix
6–5