HC1S25 Datasheet, PDF (53/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Operating Conditions
Table 4–50 shows the high-speed I/O timing for HardCopy Stratix
devices.
Table 4–50. High-Speed I/O Specifications (Part 1 of 2) Notes (1), (2)
Symbol
Conditions
f_HSCLK (Clock frequency)
(LVDS, LVPECL, HyperTransport
technology)
f_HSCLK = f_HSDR / W
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
f_HSDR Device operation
(LVDS, LVPECL, HyperTransport
technology)
J = 10
J=8
J=7
J=4
J=2
J = 1 (LVDS and LVPECL
only)
f_HSCLK (Clock frequency)
(PCML)
f_HSCLK = f_HSDR / W
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
f_HSDR Device operation (PCML) J = 10
J=8
J=7
J=4
J=2
J=1
TCCS
All
SW
PCML (J = 4, 7, 8, 10)
PCML (J = 2)
PCML (J = 1)
LVDS and LVPECL (J = 1)
LVDS, LVPECL,
HyperTransport technology
(J = 2 through 10)
Performance
Min
Typ
Max
10
210
50
231
150
420
100
462
300
717
300
840
300
840
300
840
300
840
100
462
100
462
10
100
50
200
150
200
100
250
300
400
300
400
300
400
300
400
300
400
100
400
100
250
200
750
900
1,500
500
440
Unit
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
ps
ps
ps
ps
ps
ps
Altera Corporation
September 2008
4–29