HC1S25 Datasheet, PDF (26/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Recommended Operating Conditions
Table 4–3. HardCopy Stratix Device DC Operating Conditions Note (7)
Symbol
Parameter
Conditions
I_I
I_OZ
I_CC0
R_CONF
Input pin leakage current V_I = V_CCIOmax to 0 V (8)
Tri-stated I/O pin leakage V_O = V_CCIOmax to 0 V
current
(8)
V_CC supply current
(standby) (All memory
blocks in power-down
mode)
V_I = ground, no load,
no toggling inputs
Value of I/O pin pull-up
resistor before and
during configuration
Vi=0; V_CCIO = 3.3 V (9)
Vi=0; V_CCIO = 2.5 V (9)
Vi=0; V_CCIO = 1.8 V (9)
Vi=0; V_CCIO = 1.5 V (9)
Recommended value of
I/O pin external
pull-down resistor before
and during configuration
Minimum
–10
–10
15
20
30
50
Typical
25
45
65
100
1
Maximum Unit
10
μA
10
μA
mA
50
kΩ
70
kΩ
100
kΩ
150
kΩ
2
kΩ
Notes to Tables 4–1 through 4–3:
(1) Refer to the Operating Requirements for Altera Devices Data Sheet.
(2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
(3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 V or overshoot to 4.6 V for input
currents less than 100 mA and periods shorter than 20 ns.
(4) Maximum V_CC rise time is 100 ms, and V_CC must rise monotonically.
(5) V_CCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses.
(6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before V_CCINT and V_CCIO are
powered.
(7) Typical values are for T_A = 25 °C, V_CCINT = 1.5 V, and V_CCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(8) This value is specified for normal device operation. The value may vary during power up. This applies for all V_CCIO
settings (3.3, 2.5, 1.8, and 1.5 V).
(9) Pin pull-up resistance values will be lower if an external source drives the pin higher than V_CCIO.
4–2
Altera Corporation
September 2008