HC1S25 Datasheet, PDF (96/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Performance Improvement Example
Performance
Improvement
Example
With the design used for the performance improvement example in this
section, the designer was seeking performance improvement on an
HC1S30F780 design for an intellectual property (IP) core consisting of
approximately 5200 LEs, 75,000 bits of memory, and two digital signal
processing (DSP) multiplier accumulators (MACs). The final application
needed to fit in a reserved portion of the HC1S30 device floorplan, so the
entire block of IP was initially bounded in a single LogicLock region. The
IP block was evaluated as a stand-alone block.
Initial Design Example Settings
The default settings in the Quartus II software version 4.2 were used, with
the following initial constraints added:
■ The device was set to the target Stratix FPGA device which is the
prototype for the HC1S30F780 device:
set_global_assignment -name DEVICE
EP1S30F780C6_HARDCOPY_FPGA_PROTOTYPE
■ A LogicLock region was created for the block to bound it in the
reserved region.
■ The LogicLock region properties were set to Auto Size and Floating
Location, and Reserve Unused Logic was turned on:
set_global_assignment -name LL_STATE FLOATING
set_global_assignment -name LL_AUTO_SIZE ON
set_global_assignment -name LL_RESERVED OFF
set_global_assignment -name LL_SOFT OFF
■ Virtual I/O pins were used for the ports of the core since this core
does not interface to pins in the parent design, and the I/O pins were
placed outside the LogicLock region and are represented as registers
in LEs.
The initial compilation results yielded 65.30-MHz f_MAX in the FPGA. The
block was constrained through virtual I/O pins and a LogicLock region
to keep the logic from spreading throughout the floorplan.
6–8
Altera Corporation
September 2008