HC1S25 Datasheet, PDF (8/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Stratix and Stratix FPGA Differences
The HardCopy Stratix family consists of base arrays that are common to
all designs for a particular device density. Design-specific customization
is done within the top two metal layers. The base arrays use an
area-efficient sea-of-logic-elements (SOLE) core and extend the flexibility
of high-density Stratix FPGAs to a cost-effective, high-volume production
solution. With a seamless migration process employed in numerous
successful designs, functionality-verified Stratix FPGA designs can be
migrated to fixed-function HardCopy Stratix devices with minimal risk
and guaranteed first-time success.
The SRAM configuration cells of the original Stratix devices are replaced
in HardCopy Stratix devices by metal connects, which define the function
of each logic element (LE), digital signal processing (DSP) block,
phase-locked loop (PLL), embedded memory, and I/O cell in the device.
These resources are interconnected using metallization layers. Once a
HardCopy Stratix device has been manufactured, the functionality of the
device is fixed and no re-programming is possible. However, as is the case
with Stratix FPGAs, the PLLs can be dynamically configured in
HardCopy Stratix devices.
HardCopy Stratix
and Stratix FPGA
Differences
To ensure HardCopy Stratix device functionality and performance,
designers should thoroughly test the original Stratix FPGA-based design
for satisfactory results before committing the design for migration to a
HardCopy Stratix device. Unlike Stratix FPGAs, HardCopy Stratix
devices are customized at the time of manufacturing and therefore do not
have programmability support.
Since HardCopy Stratix devices are customized within the top two metal
layers, no configuration circuitry is required. Refer to “Power-Up Modes
in HardCopy Stratix Devices” on page 2–7 for more information.
Depending on the design, HardCopy Stratix devices can provide, on
average, a 50% performance improvement over equivalent Stratix
FPGAs. The performance improvement is achieved by die size reduction,
metal interconnect optimization, and customized signal buffering.
HardCopy Stratix devices consume, on average, 40% less power than
their equivalent Stratix FPGAs.
1 Designers can use the Quartus II software to design HardCopy
Stratix devices, estimate performance and power consumption,
and maximize system throughput.
2–2
Altera Corporation
September 2008