HC1S25 Datasheet, PDF (73/110 Pages) Altera Corporation – HardCopy Stratix Device Family

How to Design HardCopy Stratix Devices
After selecting the wizard you want to run, the “HardCopy Timing
Optimization Wizard: Summary” page shows you details about the
settings you made in the Wizard, as shown in (Figure 5–4).
Figure 5–4. HardCopy Timing Optimization Wizard Summary Page
When either of the second two options in Figure 5–4 are selected
(Migration and Compilation or Full HardCopy Compilation), designs
are targeted to HardCopy Stratix devices and optimized using the
HardCopy Stratix placement and timing analysis to estimate
performance. For details on the performance optimization and estimation
steps, refer to “Performance Estimation” on page 5–12. If the performance
requirement is not met, you can modify your RTL source, optimize the
FPGA design, and estimate timing until you reach timing closure.
Tcl Support for HardCopy Migration
To complement the GUI features for HardCopy migration, the Quartus II
software provides the following command-line executables (which
provide the tool command language (Tcl) shell to run the --flow Tcl
command) to migrate the HARDCOPY_FPGA_PROTOTYPE project to
HardCopy Stratix devices:
■ quartus_sh --flow migrate_to_hardcopy <project_name> [-c
<revision>] r
This command migrates the project compiled for the
HARDCOPY_FPGA_PROTOTYPE device to a HardCopy Stratix
device.
Altera Corporation
September 2008
5–11
Preliminary