HC1S25 Datasheet, PDF (20/110 Pages) Altera Corporation – HardCopy Stratix Device Family

HardCopy Series Handbook, Volume 1
Table 3–1. HardCopy Stratix JTAG Instructions (Part 2 of 2)
JTAG Instruction
CLAMP (1)
Instruction Code
00 0000 1010
Description
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
Note to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
f
The boundary-scan description language (BSDL) files for HardCopy
Stratix devices are different from the corresponding Stratix FPGAs. The
BSDL files for HardCopy Stratix devices are available for download
from the Altera website at www.altera.com.
The HardCopy Stratix device instruction register length is 10 bits; the
USERCODE register length is 32 bits. The USERCODE registers are
mask-programmed, so they are not re-programmable. The designer can
choose an appropriate 32-bit sequence to program into the USERCODE
registers.
Tables 3–2 and 3–3 show the boundary-scan register length and device
IDCODE information for HardCopy Stratix devices.
Table 3–2. HardCopy Stratix Boundary-Scan Register Length
Device
HC1S25 672-pin FineLine BGA
HC1S30 780-pin FineLine BGA
HC1S40 780-pin FineLine BGA
HC1S60 1,020-pin FineLine BGA
HC1S80 1,020-pin FineLine BGA
Maximum Boundary-Scan Register Length
1,458
1,878
1,878
2,382
2,382
3–2
Preliminary
Altera Corporation
September 2008