HC1S25 Datasheet, PDF (56/110 Pages) Altera Corporation – HardCopy Stratix Device Family

PLL Specifications
Table 4–51. Enhanced PLL Specifications (Part 3 of 3)
Symbol
Parameter
Min Typ
Max
Unit
t_ARESET
Minimum pulse width on ARESET
10
ns
signal
(11)
500
ns
(12)
Notes to Table 4–51:
(1) The minimum input clock frequency to the PFD (f_IN/N) must be at least 3 MHz for HardCopy Stratix device
enhanced PLLs.
(2) Refer to “Maximum Input and Output Clock Rates”.
(3) t_FCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(4) This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be
driven by the logic array.
(5) Actual jitter performance may vary based on the system configuration.
(6) Total required time to reconfigure and lock is equal to t_DLOCK + t_CONFIG. If only post-scale counters and delays are
changed, then t_DLOCK is equal to 0.
(7) The VCO range is limited to 500 to 800 MHz when the spread spectrum feature is selected.
(8) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
(9) Exact, user-controllable value depends on the PLL settings.
(10) The LOCK circuit on HardCopy Stratix PLLs does not work for industrial devices below –20°C unless the PFD
frequency > 200 MHz. Refer to the Stratix FPGA Errata Sheet for more information on the PLL.
(11) Applicable when the PLL input clock has been running continuously for at least 10 µs.
(12) Applicable when the PLL input clock has stopped toggling or has been running continuously for less than 10 µs.
4–32
Altera Corporation
September 2008