HC1S25 Datasheet, PDF (40/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
f
The final timing numbers and actual performance for each HardCopy
Stratix design is available when the design migration is complete and are
subject to verification and approval by Altera and the designer during the
HardCopy Design review process.
For more information, refer to the HardCopy Series Back-End Timing
Closure chapter in the HardCopy Series Handbook.
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–1 shows the pin-to-pin timing model for bidirectional
IOE pin timing. All registers are within the IOE.
Figure 4–1. External Timing in HardCopy Stratix Devices
Dedicated
Clock
OE Register
PRN
DQ
CLRN
Output Register
PRN
DQ
CLRN
Input Register
PRN
DQ
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
Bidirectional
Pin
CLRN
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
4-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in the Stratix Device Handbook.
4–16
Altera Corporation
September 2008