HC1S25 Datasheet, PDF (97/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
The initial compile-relevant statistics for this example are provided in
Table 6–1.
Table 6–1. Initial Compilation Statistics
Result Type
f_MAX
Total logic elements (LEs)
Total LABs
M512 blocks
M4K blocks
M-RAM blocks
Total memory bits
Total RAM block bits
DSP block 9-bit elements
Results
65.30 MHz
5,187/32,470 (15%)
564/3,247 (17%)
20/295 (6%)
16/171 (9%)
0/2 (0%)
74,752/2,137,536 (3%)
85,248/2,137,536 (3%)
2/96 (2%)
The design project was migrated to the HardCopy device using the
HardCopy Timing Optimization wizard and was compiled. The default
settings of the LogicLock region in a HardCopy Stratix project in the
Quartus II software have the Soft Region option turned on. With this
setting, the HardCopy Stratix compilation yields an f_MAX of 66.48 MHz,
mainly due to the Fitter placement being scattered in an open design
(Figure 6–3). Because the Soft Region is set to on, the LogicLock region is
not bounded. This is not an optimal placement in the HardCopy Stratix
design and is not the best possible performance.
Altera Corporation
6–9
September 2008