HC1S25 Datasheet, PDF (101/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
Making these settings in the FPGA while leaving Analysis & Synthesis
Effort set to Speed yielded some additional improvement in the FPGA as
shown in Table 6–3.
Table 6–3. Results of Analysis & Synthesis Effort Set to Speed
Result Type
f_MAX
Total logic elements
Total LABs
Results
70.28 MHz
5,515/32,470 (16%)
597/3,247 (18%)
The WYSIWYG resynthesis added a minimal increase in LEs over the
speed setting, and the design performance improved by 2 MHz in the
FPGA. Using the HardCopy Timing Optimization wizard to migrate the
design to HardCopy and subsequently compiling the HardCopy Stratix
design, we find that performance is not improved beyond previous
compiles, with an f_MAX of 86.58 MHz.
The Quartus II software automatically optimizes state machines and
restructures multiplexers when these settings are set to Auto in the
Analysis & Synthesis settings. Changing these options from Auto
usually does not yield performance improvement.
For example, changing the multiplexer restructuring and state machine
processing settings from both set to Auto, to On and One-Hot,
respectively, actually hurt performance, not allowing the Quartus II
software to determine the optimization on a case-by-case basis. With
these settings, the FPGA compiled to an f_MAX of 65.99 MHz, and the
HardCopy Stratix design only performed at 83.77 MHz. For this design
example, it is better to leave these settings to Auto as seen in the Tcl
assignments in the “Using Fitter Assignments and Physical Synthesis
Optimizations for Performance Improvement” section, and allow the
Quartus II software to determine when to use these features.
Using Fitter Assignments and Physical Synthesis Optimizations
for Performance Improvement
After exploring the Analysis & Synthesis optimization settings in the
Quartus II software, you can use the Fitter Settings and Physical
Synthesis Optimization features to gain further performance
improvement in your Stratix FPGA and HardCopy Stratix devices. In this
design example, multiplexer and state machine restructuring settings
have been set to Auto, and the Synthesis Optimization Technique is set
Altera Corporation
September 2008
6–13