HC1S25 Datasheet, PDF(7/110 Page) Altera Corporation

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HC1S25 Datasheet, PDF (7/110 Pages) Altera Corporation – HardCopy Stratix Device Family

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2. Description, Architecture,

and Features

H51002-3.4

Introduction

HardCopyÂ® StratixÂ® structured ASICs provide a comprehensive

alternative to ASICs. The HardCopy Stratix device family is fully

supported by the QuartusÂ® II design software, and, combined with a vast

intellectual property (IP) portfolio, provides a complete path from

prototype to volume production. Designers can now procure devices,

tools, and AlteraÂ® IP for their high-volume applications.

As shown in Figure 2â1, HardCopy Stratix devices preserve their Stratix

FPGA counterpartâs architecture, but the programmability for logic,

memory, and interconnect is removed. HardCopy Stratix devices are also

manufactured in the same process technology and process voltage as

Stratix FPGAs. Removing all configuration and programmable routing

resources and replacing it with direct metal interconnect results in

considerable die size reduction and the ensuing cost savings.

Figure 2â1. HardCopy Stratix Device Architecture

M512 RAM Blocks for

Dual-Port Memory, Shift

Registers, & FIFO Buffers

DSP Blocks for

Multiplication and Full

Implementation of FIR Filters

M4K RAM Blocks

for True Dual-Port

Memory & Other Embedded

Memory Functions

IOEs Support DDR, PCI, GTL+, SSTL-3,

SSTL-2, HSTL, LVDS, LVPECL, PCML,

HyperTransport & other I/O Standards

IOEs

LABs

IOEs

LABs

DSP

Block

IOEs

LABs

IOEs

LABs

M-RAM Block

LABs

Altera Corporation

2â1

September 2008

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