HC1S25 Datasheet, PDF (105/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Design Guidelines for HardCopy Stratix Performance Improvement
The results of the DSE run with the Seed Sweep option are summarized
in Table 6–7.
Table 6–7. DSE Results Run with Seed Sweep
Compile Point
Base (Best)
1
2
3
4
5
6
7
8
9
10
Clock Period: CLK
10.868 ns
11.710 ns
11.040 ns
10.790 ns
10.945 ns
11.154 ns
11.707 ns
11.648 ns
11.476 ns
11.423 ns
11.449 ns
The results in Table 6–7 illustrate how the Seed Sweep option in DSE
provides additional improvement in the HardCopy Stratix design, even
after DSE has been run on the Stratix FPGA project. In this example,
compile point 3 using seed value = 4 turns out to be slightly beneficial
over other seeds in the Fitter Placement. The HardCopy Stratix device has
an f_MAX of 92.71 MHz.
Back-Annotation and Location Assignment Adjustments
Another technique available for improving performance in the
HardCopy Stratix design is manually adjusting placement and
back-annotating location assignments from the placement results. These
techniques should be one of the last steps taken for design optimization
of HardCopy Stratix devices.
Observing the floorplan of the 92.71 MHz compile (Figure 6–6), the
placement of the LogicLock region is stretched vertically, and additional
improvement is possible if the aspect ratio of the LogicLock region is
defined, and placement in it is refined.
Altera Corporation
September 2008
6–17