HC1S25 Datasheet, PDF (79/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Location
Constraints
Location Constraints
Figure 5–6. Placement Constraints Flow for HardCopy Stratix Devices
Compile the Design for
HARDCOPY_FPGA_PROTOTYPE
Migrate to HardCopy Stratix
Device Using the HardCopy
Timing Optimization Wizard
Add/Update
Placement Constraints
Add/Update
LogicLock Constraints
Compile for HardCopy
Stratix Device
No _Performance
Met?
Yes
Generate HardCopy Files
This section provides information about HardCopy Stratix logic location
constraints.
LAB Assignments
Logic placement in HardCopy Stratix is limited to LAB placement and
optimization of the interconnecting signals between them. In a Stratix
FPGA, individual logic elements (LE) are placed by the Quartus II Fitter
into LABs. The HardCopy Stratix migration process requires that LAB
contents cannot change after the Timing Optimization Wizard task is
done. Therefore, you can only make LAB-level placement optimization
and location assignments after migrating the
HARDCOPY_FPGA_PROTOTYPE project to the HardCopy Stratix
device.
Altera Corporation
September 2008
5–17
Preliminary