HC1S25 Datasheet, PDF (89/110 Pages) Altera Corporation – HardCopy Stratix Device Family

H51027-1.4
Introduction
Background
Information
6. Design Guidelines
for HardCopy Stratix
Performance Improvement
Advanced design techniques using Altera^® HardCopy^® Stratix^® devices
can yield tremendous performance improvements over the design
implemented in a Stratix FPGA device. After you verify your Stratix
FPGA design in system operation and are ready to migrate to a
HardCopy Stratix device, additional device performance is possible
through the migration. This chapter focuses on Quartus^® II software
advanced design techniques that apply to both Stratix FPGA devices and
HardCopy Stratix devices. Use these techniques to increase your
maximum clock frequency, improve input and output pin timing, and
improve timing closure in HardCopy Stratix designs.
1 Every design is different. The techniques described in this
chapter may not apply to every design, and may not yield the
same level of improvement.
This document discusses the following topics:
■ Planning Stratix FPGA design for HardCopy Stratix design
conversion
■ Using LogicLock™ regions in HardCopy Stratix designs
■ Using Design Space Explorer (DSE) on HardCopy Stratix designs
■ Design performance improvement example
To understand the Quartus II software and device architecture, and to use
the advanced design techniques described in this chapter, Altera
recommends reading the HardCopy Series Handbook and the following
chapters in the Quartus II Software Handbook:
■ Design Recommendations for Altera Devices and the Quartus II Design
Assistant
■ Design Optimization for Altera Devices
■ Design Space Explorer
■ Analyzing and Optimizing the Design Floorplan
■ Netlist Optimizations and Physical Synthesis
Altera Corporation
6–1
September 2008