HC1S25 Datasheet, PDF (44/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Timing Closure
Tables 4–38 through 4–39 show the external timing parameters on column
and row pins for HC1S40 devices.
Table 4–38. HC1S40 External I/O Timing on Column Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
2.126
ns
0.000
ns
2.856
7.253
ns
2.796
7.138
ns
2.796
7.138
ns
1.466
ns
0.000
ns
1.092
2.473
ns
1.032
2.358
ns
1.032
2.358
ns
Table 4–39. HC1S40 External I/O Timing on Row Pins Using Global Clock
Networks
Parameter
t_INSU
t_INH
t_OUTCO
t_XZ
t_ZX
t_{INS UPL L}
t_INHPLL
t_OUTCOPLL
t_XZPLL
t_ZXPLL
Performance
Unit
Min
Max
2.020
ns
0.000
ns
2.912
7.480
ns
2.939
7.562
ns
2.939
7.562
ns
1.370
ns
0.000
ns
1.144
2.693
ns
1.171
2.775
ns
1.171
2.775
ns
4–20
Altera Corporation
September 2008