HC1S25 Datasheet, PDF (92/110 Pages) Altera Corporation – HardCopy Stratix Device Family

Using LogicLock Regions in HardCopy Stratix Designs
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Altera recommends physical synthesis optimizations for the
HARDCOPY_FPGA_PROTOTYPE. The work done in the prototype
enhances performance in the HardCopy Stratix device after migration.
Duplicating combinational logic and registers can increase area
utilization, which limits placement flexibility when designs exceed 95%
logic element (LE) utilization. However, duplicating combinational logic
and registers can help with performance by allowing critical paths to be
duplicated when their endpoints must reach different areas of the device
floorplan.
For more information on netlist and design optimization, refer to Area
Optimization and Timing Closure in volume 2 of the Quartus II Development
Software Handbook.
Using LogicLock
Regions in
HardCopy Stratix
Designs
Create LogicLock regions in the HARDCOPY_FPGA_PROTOTYPE
project and migrate the regions into the HardCopy Stratix optimization
project using the Quartus II software. LogicLock regions can provide
significant benefits in design performance by carefully isolating critical
blocks of logic, including:
■ MegaCore^® IP functions
■ I/O interfaces
■ Reset or other critical logic feeding global clock lines
■ Partitioned function blocks
You must compile your design initially without LogicLock regions
present and review the timing analysis reports to determine if additional
constraints or LogicLock regions are necessary. This process allows you to
determine which function blocks or data paths require LogicLock
regions.
Create LogicLock regions in the HARDCOPY_FPGA_PROTOTYPE
design project in the Quartus II software. This transfers the LogicLock
regions to the HardCopy design project after the HardCopy Timing
Optimization Wizard is run. Although the Quartus II software transfers
the contents of the LogicLock region, the area, location, and soft
boundary settings revert to their default settings in the HardCopy project
immediately after the HardCopy Timing Optimization Wizard is run.
If you are using LogicLock regions, Altera recommends you use the
Migration Only setting in the HardCopy Timing Optimization Wizard to
create the HardCopy design project. You should not compile your design
automatically using the Full Compilation or Migrate and Compile
options in the wizard. Open the HardCopy design project and verify that
the LogicLock region properties meet your desired settings before
compiling the HardCopy optimization project. LogicLock soft regions are
6–4
Altera Corporation
September 2008